Owing to its higher electron mobility, gallium arsenide (GaAs) is thought to have potential for outperforming silicon devices in digital integrated circuits. To achieve high performance, GaAs must be able to incorporate adequate amounts of high-speed memory on chip. High speed GaAs microprocessors developed to date have integrated only small amounts of memory on chip. Future designs will require large sub-2 ns on-chip caches.
Technology Description
University of Michigan researchers have developed a new memory cell architecture for GaAs MESFETs. This access current increase improves access time by about 25-50% in memory arrays of 4kb to 16kb. This new cell is immune to the possibility of destructive read associated with conventional cells. The biasing of this cell minimizes the impact of leakage currents on the number of bits that can be safely connected to a column. Measurements indicate this SRAM can work with up to 512 bits per column for 75Y'C operation. In addition to having faster read times, this cell can be written to much faster than conventional memory cells. A memory has been simulated and designed around this new cell, and preliminary tests have been conducted. The University seeks to license this technology for the development and commercialization of products.
Applications
• On-chip cache memories, test equipment,graphics and signal processors
Advantages
• Faster read and write speeds
• Removes the write after read hazardof the conventional cell architecture
• Eliminates the need to limit bit-lineswing during read
Nombre: Rodriguez B. Joiver I.
Asignatura: EES
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